Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme

Low Power Flash ADC

In this paper, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1GHz, is implemented in a 1.2 V analog supply voltage. HSpice simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes less power i n a commercial 90n...

A Low-Power, Small-Size 10-Bit Successive-Approximation ADC

A new Successive-Approximation ADC (Analog-toDigital Converter) was designed which not only consumes little power, but also requires a small chip area. To achieve those goals, both comparator and internal DAC (Digital-to-Analog Converter) have been improved. The ADC was designed in a 1.2 μm CMOS double-poly double-metal n-well process. It performs 10-bit conversion with 67 dB SFDR. Power consum...

Low Power, 3-bit CMOS Pipeline ADC with Reduced Complexity Flash Architecture

A 3-bit, 2-V pipeline analog-to-digital converter has been designed using a modified flash architecture. The developed circuit blocks of the modified flash analog-todigital converter, operating at 135MHz, are a fully differential comparator, a digital-to-analog converter and a sample-and-hold amplifier. The design technique of the N-bit modified flash ADC requires only 2 1) comparators as compa...

Design of a 45nm TIQ Comparator for High Speed and Low Power 4-Bit Flash ADC

The continued speed improvement of serial links and appearance of new communication technologies, such as ultra-wideband (UWB), have introduced increasing demands on the speed and power specifications of high-speed low-tomedium resolution analog-to-digital converters (ADCs).This paper presents the design of high speed and ultra low power comparator of a 4-bit ADC. The comparator used is Thresho...

Low Power Encoder and Comparator Design of 5-bit Flash Adc